1. Field of the Invention
The present invention relates to a method of forming a transistor using selective epitaxial growth (SEG), and more specifically, to a method of forming a transistor having a raised source/drain using selective epitaxial growth.
2. Description of the Prior Art
The selective epitaxial growth technology is widely applied in manufacturing a lot of kinds of semiconductor devices, such as a metal oxide semiconductor (MOS) transistor having a raised source/drain. The selective epitaxial growth technology is used to form an epitaxial layer on a single-crystalline substrate, and a crystalline orientation of the epitaxial layer is almost the same as that of the substrate. Additionally, before the epitaxial layer is deposited on the substrate, a surface cleaning process must be performed to remove native oxides and other impurities from a surface of the substrate so that the epitaxial layer of a good quality can be obtained. Accordingly, the surface cleaning process plays an important role in the selective epitaxial growth technology.
Please refer to FIG. 1 to FIG. 4. FIG. 1 to FIG. 4 are schematic diagrams illustrating a prior art method of forming a transistor using selective epitaxial growth. As shown in FIG. 1, a plurality of shallow trench isolations (STIs) 12 is formed in a silicon substrate 10. Then, a gate oxide layer 14 is formed on a portion of the silicon substrate 10 and a gate electrode 16 is formed on the gate oxide layer 14. Usually, the gate oxide layer 14 and the gate electrode 16 comprise silicon dioxide (SiO2) and doped polysilicon respectively. Thereafter, the gate electrode 16 is used as a mask layer and a first ion implantation process is performed to implant low dosage of dopants 18 into the silicon substrate 10, thereby forming source/drain extensions 20 in the silicon substrate 10 adjacent to both sidewalls of the gate electrode 16.
As shown in FIG. 2, a silicon dioxide layer 22 is formed on a surface of the silicon substrate 10 and covers the gate electrode 16. Then, a silicon nitride layer 24 is formed on the silicon dioxide layer 22. Subsequently, an etching-back process is performed on the silicon nitride layer 24 and the silicon dioxide layer 24 to form a spacer 25 on each sidewall of the gate electrode 16.
As shown in FIG. 3, the gate electrode 16 and the spacer 25 together function as a mask layer, and a second ion implantation process is performed to implant high dosage of dopants 26 into the silicon substrate 10, thus forming shallow source/drain 28 in the silicon substrate 10. Following that, a thermal annealing process is performed to activate the dopants in the silicon substrate 10 and repair the crystalline defects of the silicon substrate 10 that are formed while the above-mentioned ion implantation processes are performed. Usually, a temperature of the thermal annealing process ranges from 1000° C. to 1050° C.
As shown in FIG. 4, a surface cleaning process is performed to dip the silicon substrate 10 into a hydrofluoric (HF) acid that removes native oxides and other impurities from the surface of the silicon substrate 10. Then, a hydrogen-baking step is performed to bake the silicon substrate 10 for about 2 minutes in the hydrogen ambience and at a temperature higher than 850° C. The high-temperature hydrogen can react with native oxides and impurities that are not removed by the surface cleaning process for cleaning the surface of the silicon substrate 10 again. Thereafter, a selective epitaxial growth process is performed to deposit a silicon epitaxial layer 30 on each source/drain 28 and form a silicon epitaxial layer 32 on a top surface of the gate electrode 16, thereby completing the manufacture of the transistor 40. Additionally, the silicon epitaxial layers 30 are used as a raised source/drain of the transistor 40.
It should be noted that the etching-back process for forming the spacer 25 usually leaves several impurities, such as carbon atoms, fluorine atoms, hydrogen atoms, and so on, on the surface of the silicon substrate 10. The carbon atoms among the impurities always lead to forming pits 30a in the silicon epitaxial layers 30, and more seriously, the impurities may cause that the silicon epitaxial layers 30 cannot be formed on the silicon substrate 10. However, the prior art surface cleaning process cannot remove carbon, fluorine, and hydrogen atoms effectively, so that the silicon epitaxial layers 30 always contain pits 30a and the quality of the silicon epitaxial layers 30 is usually poor. Furthermore, since the prior art surface cleaning process cannot remove the impurities from the silicon substrate 10 completely, the temperature and the processing time of the hydrogen-baking step have to be increased in order to remove the impurities. However, for the transistor 40 having the ultra shallow source/drain 28, increasing the temperature and the processing time of the hydrogen-baking step will make the shallow source/drain 28 over-diffuse, thereby increasing leakage currents of the transistor 40 and reducing electrical performance of the transistor 40. Moreover, as shown in FIG. 4 and FIG. 5, the hydrofluoric acid always erodes the silicon oxide layer 22 to form an undercut on a bottom of the spacer 25, which leads to leakage currents of the transistor 40.